Phase-locked loop

Many electronic systems use internal clocks which\nare required to be phase-aligned to and/or frequency multiples of some\nexternal reference clock. For example, a typical PC CPU might have\nan internal 2.4 GHz clock which is phase aligned to a bus clock\nrunning at 100 MHz. The frequency multiplication is important because\nmultiplying frequencies on chip is much easier than transmitting 2.4\nGHz clocks on a motherboard. The phase alignment is important so that\ndata can be exchanged reliably between circuits in the 2.4 GHz core\ndomain and circuits in the 100 MHz bus clock domain. Typically, the reference clock enters the chip and drives a phase\nlocked loop (PLL), which then drives the system's clock\ndistribution. The clock distribution is usually balanced so that the\nclock arrives at every endpoint simultaneously. One of those endpoints\nis the PLL's feedback input. The function of the PLL is to compare\nthe distributed clock to the incoming reference clock, and vary the\nphase and frequency of its output until the reference and feedback\nclocks are phase and frequency matched. PLLs are ubiquitous -- they tune clocks in systems several feet\nacross, as well as clocks in small portions of individual\nchips. Sometimes the reference clock may not actually be a pure clock\nat all, but rather a data stream with enough transitions that the PLL\nis able to recover a regular clock from that stream. Sometimes the\nreference clock is the same frequency as the clock driven through the\nclock distribution, other times the distributed clock may be some\nrational multiple of the reference. PLLs are generally built of a phase frequency detector, a charge pump,\nlow pass filter, bias generator, voltage-controlled oscillator (VCO),\nand usually some kind of output converter. There may be a divider\nin the feedback path or in the reference path, or both, in order to\nmake the PLL's output clock a rational multiple of the reference. One desirable property of all PLLs is that the reference and feedback\nclock edges be brought into very close alignment. The average difference\nin time between the phases of the two signals when the PLL has achieved\nlock is called the static phase offset. The variance between these\nphases is called tracking jitter. Ideally, the static phase offset\nshould be zero, and the tracking jitter should be as low as possible. Another desirable property of all PLLs is that the phase and frequency\nof the generated clock be unaffected by rapid changes in the voltages\nof the power and ground supply lines, as well as the voltage of the\nsubstrate on which the PLL circuits are fabricated. This is called\nsupply and substrate noise rejection. Phase-locked loops are widely used for synchronization purposes; in space communications for coherent carrier tracking and threshold extension, bit synchronization, and symbol synchronization. Phase-locked loops can also be used to demodulate frequency-modulated signals, and to synthesize new frequencies which are a multiple of a reference frequency. An important part of a phase-locked loop is the phase detector. This compares the phase of the local oscillator to that of the reference signal. In an analog PLL the phase detector is a linear multiplier. This generates a low-frequency signal whose amplitude is related to the phase difference, or phase error, between the oscillator and the reference, and an unwanted high-frequency signal that is filtered out. There are several types of phase detectors used in digital phase-locked loops. The simplest is an exclusive OR gate, which maintains a 90° phase difference, but cannot lock the signal unless it is already on frequency. A more complicated one uses flip-flops to determine which of the two signals has a zero-crossing earlier or more often. This brings the signal in even when it is off frequency.

Analog phase-locked loop

The equations governing a phase-locked loop are the following:\n:\n:\n:\nwhere \n:\nthe input to the PLL is , the output of the voltage-controlled oscillator (VCO) is , the output of the phase detector is . The input to the loop filter is , the output is . Note that is the sensitivity of the VCO and is expressed in Hz/V. We can deduce how the PLL reacts to a sinusoidal input signal:\n:\nThe output of the phase detector then is:\n:\nThis can be rewritten into sum and difference components using trigonometric identities:\n:\nFiltering out the sum frequency and leaving the difference frequency, enables us to derive a small-signal model of the phase-locked loop. If we can make , then the can be approximated by its argument: . The phase-locked loop is said to be locked if this is the case. Some parts of this article are derived from public domain parts of Federal Standard 1037C in support of MIL-STD-188.